Capacitive load driving amplifier

ABSTRACT

An electronic amplifier for driving a capacitive load may include first and second differential input terminals to receive an input signal, and first and second differential output terminals to provide a differential output signal. The amplifier may further include a first operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the first differential output terminal, and a second operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the second differential output terminal. The first and second operational devices may be operatively configured so that both the first and the second output terminals are at a same reference potential during periods in which a module of differential output signal amplitude decrease.

FIELD OF THE INVENTION

The present invention relates to electronic amplifying devices, and inparticular, to a capacitive load driving amplifier.

BACKGROUND OF THE INVENTION

In recent electronic amplifiers devised to drive a capacitive load, forexample, in audio amplifiers usable in battery-operated portabledevices, there may be a need to have reduced current consumption. Aknown electronic amplifier usable to drive a capacitive load generallycomprises a differential amplifier, which includes differential inputterminals to receive an input signal Vin, for example, a substantiallysinusoidal voltage signal. In addition, the differential amplifieroperates to amplify the input signal Vin in order to provide first V1and second V2 output voltages to respective differential outputterminals of the amplifier. The first V1 and second V2 output voltageshave opposite polarity in respect to a common mode voltage VCM.

The differential amplifier is powered from a power supply potential VDDand a ground GND potential, the common mode voltage VCM is in the middlebetween the power supply VDD and ground GND in order to reach maximumswing of a differential output signal Vout=V1-V2. The differentialamplifier described comprises an output stage which drives thecapacitive load. Particularly, the output stage is so configured thatenergy from the power supply potential VDD is consumed both duringcharging periods of the capacitive load and during discharging periodsas well. In fact, conduction of output transistors forming the outputstages of the differential amplifier is handled during the mentionedcharging/discharging periods so that to define with the capacitive loaditself a conduction path for the current flowing from the power supplypotential VDD and the ground potential GND both in the charging periodsand in the discharging periods. Therefore, when the differentialamplifiers are used in portable device, a large amount of currentconsumption may reduce the life of the power supply batteries, therebycompromising the portability of the device itself.

SUMMARY OF THE INVENTION

An object is to provide an electronic amplifier for driving a capacitiveload that may overcome the drawbacks and limits of the known amplifiers,particularly with reference to current consumption.

This object is achieved by an electronic amplifier for driving acapacitive load. The electronic amplifier may include first and a seconddifferential input terminals configured to receive an input signal,first and second differential output terminals configured to provide adifferential output signal to the capacitive load, and a firstoperational device having first and second differential inputs connectedto the first and second differential input terminals, respectively, andan output connected to the first differential output terminal. Theelectronic amplifier may include a second operational device havingfirst and second differential inputs connected to the first and secondinput terminals, respectively, and an output connected to the seconddifferential output terminal. The first and second ended operationaldevices may be configured to provide the first and second differentialoutput terminals at a reference voltage during periods where anamplitude of the differential output signal decreases.

BRIEF DESCRIPTION OF THE DRAWINGS

The characteristics and the advantages of the present electronicamplifier may be better understood from the following detaileddescription of one embodiment thereof, which is given by way ofillustrative and non-limiting example with reference to the annexeddrawings, in which:

FIG. 1 shows a circuit block diagram of an electronic amplifier inaccordance with the present invention;

FIG. 2 shows a circuit diagram of an output stage of the electronicamplifier of FIG. 1;

FIGS. 3A-D show the circuit diagram of FIG. 2 schematically indicatingan output voltage on a capacitive load and currents involved insuccessive functioning periods of the electronic amplifier of FIG. 1;

FIGS. 4A-D show, with respect to a pulsation, waveforms of the outputvoltage on the capacitive load and the current from the power supplyrelated to the periods of FIGS. 3A-D; and

FIGS. 5A-C show schematically, with respect to a pulsation, waveforms ofoutput voltages associated to the electronic amplifier of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A circuit block diagram of a preferred embodiment of an electronicamplifier 100 of the invention can be described with reference toFIG. 1. It may be noted that this electronic amplifier 100 can beintegrated on a chip of semiconductor material or can be formed ofdiscrete components. In addition, the electronic amplifier 100 can bepreferably used for driving a capacitive load C the as, for example, apiezoelectric actuator. The electronic amplifier 100 is suitable todrive as well piezoelectric loudspeakers, for example in portabledevices, fire alarms, etc.

The electronic amplifier 100 can be used both for amplifying alternatingcurrent (AC) signals with or without a direct current (DC) offset. Theamplifier 100 is capable to amplify both sinusoidal signals, i.e.comprising only one harmonic, or signals including a plurality ofharmonics. The electronic amplifier 100 comprises a differential inputport including first IN1 and second IN2 input terminals to receive aninput differential signal Vin, for example, a substantially sinusoidalsignal of the audio type having peak-to-peak amplitude equal to 2V_(in).Moreover, the amplifier 100 also comprises a differential output portincluding first OUT1 and second OUT2 output terminals so that thecapacitive load C to be driven is connected between the outputterminals.

In more detail, the electronic amplifier 100 comprises first 101 andsecond 102 operational devices or power amplifiers each provided withdifferential inputs. Particularly, the first operational device 101comprises a first S− differential input connected to the first inputterminal IN1 through a first resistor R1 and a second S+ differentialinput connected to the second input terminal IN2 through a secondresistor R2.

Analogously, the second operational device 102 comprises a further firstT+ differential input connected to the first input terminal IN1 througha third resistor R3 and a further second T− differential input connectedto the second input terminal IN2 through a fourth resistor R4. It shouldbe observed that the electronic amplifier 100 is arranged so thatresistors R1, R2, R3, R4 might be equal to one another, but generallythe resistors are different.

In addition, both the first 101 and the second 102 operational devicescomprise a respective power supply terminal connected to a power supplypotential VDD, provided for example, by a battery, and a referenceground terminal to be connected to a ground potential GND.

A shown in FIG. 1, the first differential input S− of the firstoperational device 101 is connected to the first output terminal OUT1through a further first resistor R1′, which represents a feedbackresistor for the first operational device 101. The second S+differentialinput of the first operational device 101 is connected to the groundpotential GND through a further second resistor R2′.

Analogously, the further first T+ differential input of the secondoperational device 102 is connected to the ground potential GND througha further third resistor R3′. The further second differential input T−of the second operational device 102 is connected to the second outputterminal OUT2 through a further fourth resistor R4′, which represents afeedback resistor for the second operational device 102. The first 101and the second 102 operational devices of the electronic amplifier 100are single-ended amplifiers with their outputs corresponding to thefirst OUT1 and the second OUT2 output terminals, respectively.

It may be observed that the further resistors R1′, R2′, R3′, R4′ of theelectronic amplifier 100 are arranged so that ratios of each resistanceof the resistors R1′, R2′, R3′, R4′ with the corresponding resistance ofthe resistors R1, R2, R3, R4, are equal, i.e.R1′/R1=R2′/R2=R3′/R3=R4′/R4. In addition, further resistors R1′, R2′,R3′, R4′ are generally different to one another, but might be equal,i.e. R1′=R2′=R3′=R4′.

The operational devices 101 and 102 operate so that the firstoperational device 101 can deliver to the first output terminal OUT1 afirst amplified signal V1 referred to ground GND starting from the inputsignal Vin applied to its inputs, S+, S−. Analogously, the secondoperational device 102 is suitable to deliver to the second outputterminal OUT2 a second amplified signal V2 referred to ground GNDstarting from the input signal Vin applied to its corresponding inputsT+, T−.

As known by those skilled in the art, both the first 101 and second 102operational devices provide a signal voltage amplification that can beset by the value of resistors R and R′. FIGS. 5A and 5B show, withrespect a pulsation, waveforms of the first V1 and second V2 outputvoltage amplified signals provided in the first OUT1 and second OUT2output terminals, respectively.

It should be observed that the electronic amplifier 100 comprises acommon mode voltage value VCM that can be calculated as VCM=(V1+V2)/2,where V1 and V2 are output nodes' voltages above mentioned. If nodifferential input signal is applied in the input ports IN1, IN2, boththe first output terminal OUT1 and the second output terminal OUT2 areequal to low output rail GND. If, on the contrary, an input differentialsignal Vin is applied to the input port IN1, IN2, one of the operationaldevices keeps its output at low rail GND, while the other operates toamplify the input signal so that its output voltage tends to be in arange between the ground potential GND and the power supply potentialVDD, depending on the amplitude of the input signal Vin and voltagegain.

The electronic amplifier 100 provides, at the output terminalsOUT1,OUT2, an amplified differential output voltage signal Vout=V1-V2starting from the differential input signal Vin applied to the inputport IN1, IN2, which is in accordance to the following equation:Vout=(−R′/R)Vin; where −R′/R=−R1′/R1=−R2′/R2=−R3′/R3=−R4′/R4 can beapplied.

A waveform of the differential output voltage signal Vout is representedin FIG. 5C as a function of pulsation. FIG. 2 illustrates schematicallya circuit diagram of an output stage of the electronic amplifier 100.Particularly, the output stage comprises first 1011 and second 1021output stages of the inverting type, associated to the first 101 and tothe second 102 operational devices, respectively. In FIG. 2, the first101 and second 102 operational devices are schematically indicated bytriangles with their outlines in broken lines.

The first 1011 and second 1021 output stages are connected between thepower supply potential VDD and the ground potential GND. In more detail,the first output stage 1011 comprises a first M1 (P-MOS) and a second M3(N-MOS) MOS transistors connected to one another by way of theirrespective drain terminals. Similarly, the second output stage 1021comprises a third M2 (P-MOS) and a fourth M4 (N-MOS) MOS transistorsconnected to one another through their respective drain terminals.

Particularly, it may be noted that the drain terminals of these firstM1, second M3, and third M2, fourth M4 transistors correspond to thefirst OUT1 and second OUT2 output terminals of the electronic amplifier100, respectively. Therefore, the capacitive load C is connected betweenthe drain terminals.

When one of the previous transistors M1, M2, M3, M4 is “activated”, itmeans that the transistor does contribute to forming of the amplifiersoutput signal. On the other side, when one of the transistors M1, M2,M3, M4 is “deactivated”, it means that the transistor does notcontribute to forming of the amplifiers output signal, i.e. it is inquiescent condition.

With reference to FIGS. 3A-D and FIGS. 4A-D, the differential outputvoltage signal Vout=V1-V2 provided by the amplifier 100 to thecapacitive load C and corresponding charging/discharging current signalsinvolved in the first 1011 and second 1021 output stages at a transistorlevel are analyzed in detail. As an example, it is assumed that theoutput signal Vout is a sinusoidal signal divided into four quarters ofits period from 0 to □□ radian as indicated in FIGS. 4A-D. It may beobserved that the differential output voltage Vout has a peak-to-peakamplitude lower than 2VDD.

Moreover, in FIGS. 3A-D currents flowing through transistors M1, M3, M2,M4 and the capacitive load C during each of quarter of period from 0 to□□ radian are drawn. One of the currents, Ibatt, is taken from the powersupply potential VDD to charge the capacitive load C. The waveform ofcurrent Ibatt is schematically represented in FIGS. 4A-D.

With reference to FIGS. 3A and 4A, from 0 to □{tilde over ( )}□ . . .radian. P-MOS transistor M1 of the first output stage 1011 and N-MOStransistor M4 of the second output stage 1021 are both “activated”,while transistors M3 and M2 are both “deactivated”. Therefore, thecapacitive load C is charged from power supply potential VDD by thecurrent Ibatt. In the quarter of period, the output voltage Vout risesand current Ibatt decreases from its nominal value to zero correspondingto the condition of capacitive load C fully charged.

With reference to FIGS. 3B and 4B, from □{tilde over ( )}□ to □.radians,N-MOS transistor M3 of the first output stage 1011 and N-MOS transistorM4 of the second output stage 1021 are both “activated”, whiletransistors M1 and M2 are “deactivated”. Therefore, the capacitive loadC is short circuited to the ground potential GND so that to bedischarged by a discharging current ID. In the quarter of period, theoutput voltage Vout decreases and current Ibatt is maintained null.

With reference to FIGS. 3C and 4C, from □ . . . to 3□{tilde over ( )}2radians, P-MOS transistor M2 of the second output stage 1021 and N-MOStransistor M3 of the first output stage 1011 are both “activated”, whiletransistors M1 and M4 are “deactivated”. In this case, the capacitiveload C is charged from power supply potential VDD by the current Ibatt.In the quarter of period, the output voltage Vout is inverted and rises,particularly the absolute value of Vout rises, while the current Ibattdecreases from its nominal value to zero corresponding to the conditionof capacitive load C fully charged.

With reference to FIGS. 3D and 4D, from 3□{tilde over ( )}□. to 2□radian, N-MOS transistor M3 of the first output stage 1011 and N-MOStransistor M4 of the second output stage 1021 are both “activated” andremaining transistors M1 and M2 are “deactivated”. The capacitive load Cis short circuited to the ground potential GND so that to be dischargedby a further discharging current ID'. In the quarter of period, theabsolute value of output voltage Vout decreases and current Ibatt ismaintained null.

In other words, during periods in which a module of amplitude ofdifferential output signal Vout decreases, the first 101 and second 102operational devices of electronic amplifier 100 are configured to sinkone node of the capacitive load C to the same reference ground potentialGND, by activating a sinking transistor, for example, N-MOS M3 of thefirst operational device 101, when the load C is being discharged by acorresponding sinking N-MOS transistor M4 of the second operationaldevice 102. In this way, the capacitive load C is discharged at the sametime by the two sinking transistors of both operational devices 101, 102and the power involved in discharge is dissipated by these transistors.

It should be observed that even if only one sequence of driving thecapacitive load C by an alternate current signal has been described, theabove considerations are also valid for further driving sequences.Advantageously, the proposed electronic amplifier 100 consumes inaverage only ideally half of the Ibatt current provided by the powersupply potential VDD compared to the current consumption infully-differential amplifiers known in the art.

It may be noted that the current consumption savings associated to theamplifier 100 of this disclosure produce the advantage of reducing theenergy dissipation of the amplifier integrated circuitry, and therefore,reducing a overall overheating of the integrated circuitry. That ensuresreduced requirements for cooling of the proposed electronic amplifier100, and the reliability of the same amplifier is increased. It shouldbe observed that the proposed electronic amplifier 100 can be used fordriving a capacitive load C with any signal which changes in time, itmans also alternate current signals.

The electronic amplifier 100 of the present disclosure can be used inelectronic apparatuses, the as mobile phones, PDAs (Personal DigitalAssistant), clocks, alarm clocks, laptops to operate as a driver for apiezoelectric actuator or a piezoelectric speaker embedded in theapparatuses to create vibrations or sounds, respectively. The proposedelectronic amplifier 100 can also be used in further electronicapparatuses for creating ultrasound, for example, medical ultrasoundequipment and ultrasound air humidifiers.

1-11. (canceled)
 12. An electronic amplifier for driving a capacitiveload, the electronic amplifier comprising: first and a seconddifferential input terminals configured to receive an input signal;first and second differential output terminals configured to provide adifferential output signal to the capacitive load; a first operationaldevice having first and second differential inputs connected to saidfirst and second differential input terminals, respectively, and anoutput connected to said first differential output terminal; and asecond operational device having first and second differential inputsconnected to said first and second differential input terminals,respectively, and an output connected to said second differential outputterminal; said first and second operational devices being configured toprovide said first and second differential output terminals at areference voltage during periods where an amplitude of the differentialoutput signal decreases.
 13. The electronic amplifier according to claim12 wherein said first and second operational devices each comprises anoperational amplifier.
 14. The electronic amplifier according to claim12 further comprising first and second resistors configured to couple,respectively, said first and second differential inputs of said firstoperational device to said first and second differential inputterminals.
 15. The electronic amplifier according to claim 14 furthercomprising third and fourth resistors configured to couple,respectively, said first and second differential inputs of said secondoperational device to said first and second differential inputterminals.
 16. The electronic amplifier according to claim 15 whereinsaid first resistor, said second resistor, said third resistor, and saidfourth resistor have differing resistance values.
 17. The electronicamplifier according to claim 15 wherein said first resistor, said secondresistor, said third resistor, and said fourth resistor have equalresistance values.
 18. An electronic amplifier for driving a capacitiveload, the electronic amplifier comprising: first and second differentialinput terminals configured to receive an input signal; first and seconddifferential output terminals configured to provide a differentialoutput signal to the capacitive load; a first single ended operationaldevice having first and second differential inputs and an outputconnected to said first differential output terminal; first and secondresistors configured to couple, respectively, said first and seconddifferential inputs of said first single ended operational device tosaid first and second differential input terminals; a second singleended operational device having first and second differential inputsconnected to said first and second differential input terminals,respectively, and an output connected to said second differential outputterminal; third and fourth resistors configured to couple, respectively,said first and second differential inputs of said second single endedoperational device to said first and second differential inputterminals; a fifth resistor configured to connect said firstdifferential output terminal to said first differential input of saidfirst single ended operational device; a sixth resistor configured toconnect said second differential output terminal to said seconddifferential input of said second single ended operational device; aseventh resistor configured to connect said second differential input ofsaid first single ended operational device to a reference voltage; andan eighth resistor configured to connect said first differential inputof said second single ended operational device to the reference voltage;the ratio of a resistance value of said fifth resistor over a resistancevalue of said first resistor being equal to the ratio of a resistancevalue of said seventh resistor over a resistance value of said secondresistor and also being equal to the ratio of a resistance value of saidsixth resistor over a resistance value of the fourth resistor.
 19. Theelectronic amplifier according to claim 18 wherein said first resistor,said second resistor, said third resistor, and said fourth resistor havediffering resistance values.
 20. The electronic amplifier according toclaim 18 wherein said first resistor, said second resistor, said thirdresistor, and said fourth resistor have equal resistance values.
 21. Theelectronic amplifier according to claim 18 wherein said fifth resistor,said sixth resistor, said seventh resistor, and said eighth resistorhave differing resistance values.
 22. The electronic amplifier accordingto claim 18 wherein said fifth resistor, said sixth resistor, saidseventh resistor, and said eighth resistor have equal resistance values.23. The electronic amplifier according to claim 18 wherein said firstand second singled ended operational devices are configured torespectively deliver to said first and second differential outputterminals first and second amplified signals based upon the input signalthe reference voltage.
 24. The electronic amplifier according to claim19 wherein said first and second differential output terminals areconfigured to provide the differential output signal based upon theequation Vout=(−R′/R)Vin; and wherein where−R′/R=−R1′/R1=−R2′/R2=−R3′/R3=−R4′/R4.
 25. The electronic amplifieraccording to claim 18 wherein said first singled ended operationaldevice includes first and second transistors both connected to saidfirst differential output terminal via respective conduction terminals;and wherein said second singled ended operational device includes thirdand fourth transistors connected to said second differential outputterminal via respective conduction terminals.
 26. An electronicapparatus comprising an electronic amplifier configured to operate as adriver for at least one of a piezoelectric actuator and an embeddedpiezoelectric speaker, the electronic amplifier comprising: first and asecond differential input terminals configured to receive an inputsignal; first and second differential output terminals configured toprovide a differential output signal to the at least one of apiezoelectric actuator and an embedded piezoelectric speaker; a firstoperational device having first and second differential inputs connectedto said first and second differential input terminals, respectively, andan output connected to said first differential output terminal; and asecond operational device having first and second differential inputsconnected to said first and second differential input terminals,respectively, and an output connected to said second differential outputterminal; said first and second operational devices being configured toprovide said first and second differential output terminals at areference voltage during periods where an amplitude of the differentialoutput signal decreases.
 27. The electronic apparatus according to claim26 wherein said first and second operational devices each comprises anoperational amplifier.
 28. The electronic apparatus according to claim26 further comprising first and second resistors configured to couple,respectively, said first and second differential inputs of said firstoperational device to said first and second differential inputterminals.
 29. The electronic apparatus according to claim 28 furthercomprising third and fourth resistors configured to couple,respectively, said first and second differential inputs of said secondoperational device to said first and second differential inputterminals.
 30. The electronic apparatus according to claim 26 furthercomprising at least one of a mobile phone, a personal digital assistant,a clock, an alarm clock, a laptop, medical ultrasound equipment, and anultrasound air humidifier.